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GS81302T06 Datasheet, PDF (10/29 Pages) GSI Technology – 144Mb SigmaDDRTM-II+ Burst of 2 SRAM | |||
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GS81302T06/11/20/38E-500/450/400/350
Burst of 2 Byte Write Clock Truth Table
BW
BW
Current Operation
Kâ
Kâ
Kâ
(tn + 1)
(tn + 1½)
(tn)
T
T
Write
Dx stored if BWn = 0 in both data transfers
T
F
Write
Dx stored if BWn = 0 in 1st data transfer only
F
T
Write
Dx stored if BWn = 0 in 2nd data transfer only
F
F
Write Abort
No Dx stored in either data transfer
Notes:
1. â1â = input âhighâ; â0â = input âlowâ; âXâ = input âdonât careâ; âTâ = input âtrueâ; âFâ = input âfalseâ.
2. If one or more BWn = 0, then BW = âTâ, else BW = âFâ.
Burst of 2 Nybble Write Clock Truth Table
NW
NW
Current Operation
Kâ
Kâ
Kâ
(tn + 1)
(tn + 1½)
(tn)
T
T
Write
Dx stored if NWn = 0 in both data transfers
T
F
Write
Dx stored if NWn = 0 in 1st data transfer only
F
T
Write
Dx stored if NWn = 0 in 2nd data transfer only
F
F
Write Abort
No Dx stored in either data transfer
Notes:
1. â1â = input âhighâ; â0â = input âlowâ; âXâ = input âdonât careâ; âTâ = input âtrueâ; âFâ = input âfalseâ.
2. If one or more NWn = 0, then NW = âTâ, else NW = âFâ.
D
Kâ
(tn + 1)
D1
D1
X
X
D
Kâ
(tn + 1½)
D2
X
D2
X
D
Kâ
(tn + 1)
D1
D1
X
X
D
Kâ
(tn + 1½)
D2
X
D2
X
Rev: 1.03c 11/2011
10/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
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