GS8170DW36C Datasheet, PDF (8/27 Pages) GSI Technology – 18Mb Σ1x1Dp CMOS I/O Double Late Write SigmaRAM

GS8170DW36/72C-333/300/250/200
Special Functions
Burst Cycles
Although SRAMs can sustain 100% bus bandwidth by eliminating the bus turnaround cycle in Double Late Write mode, burst read
or burst write cycles may also be performed. SRAMs provide an on-chip burst address generator that can be utilized, if desired, to
simplify burst read or write implementations. The ADV control pin, when driven high, commands the SRAM to advance the
internal address counter and use the counter generated address to read or write the SRAM. The starting address for the first cycle in
a burst cycle series is loaded into the SRAM by driving the ADV pin low, into Load mode.
CK
Address
ADV
E1
W
DQA0–DQA8
CQ
SigmaRAM Pipelined Burst Reads with Counter Wraparound
Read A
Cont A+1
Cont A+2
Cont A+3
Cont A
A
Deselect
Q(A)
Q(A+1)
Q(A+2)
Q(A+3)
Q(A)
SigmaRAM Double Late Write SRAM Burst Writes with Counter Wrap-around
W rite
Continue
Continue
Continue
Continue
CK
Address
A2
XX
XX
XX
XX
XX
I nternal
A2
A3
A0
A1
A2
Address
ADV
Counter Wraps
/E1
/W
DQ
D2
D3
D0
D1
D2
CQ
Rev: 2.04 5/2005
8/27
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2002, GSI Technology, Inc.