GS8170DW36C Datasheet, PDF (24/27 Pages) GSI Technology – 18Mb Σ1x1Dp CMOS I/O Double Late Write SigmaRAM

GS8170DW36/72C-333/300/250/200
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter
Symbol
Min.
Max.
Unit Notes
1.8 V Test Port Input High Voltage
V_IHJ2
0.6 * V_DD
V_DD +0.3
V
1
1.8 V Test Port Input Low Voltage
TMS, TCK and TDI Input Leakage Current
TMS, TCK and TDI Input Leakage Current
TDO Output Leakage Current
V_ILJ2
–0.3
I_INHJ
–300
I_INLJ
–1
I_OLJ
–1
0.3 * V_DD
1
100
1
V
1
uA
2
uA
3
uA
4
Test Port Output High Voltage
V_OHJ
1.7
—
V 5, 6
Test Port Output Low Voltage
V_OLJ
—
0.4
V 5, 7
Test Port Output CMOS High
V_OHJC V_DDQ – 100 mV
—
V 5, 8
Test Port Output CMOS Low
V_OLJC
—
100 mV
V 5, 9
Notes:
1. Input Under/overshoot voltage must be –2 V > Vi < V_DDn +2 V not to exceed 2.5 V maximum, with a pulse width not to exceed 20% tTKC.
2. V_ILJ ≤ V_IN ≤ V_DDn
3. 0 V ≤ V_IN ≤ V_ILJn
4. Output Disable, V_OUT = 0 to V_DDn
5. The TDO output driver is served by the V_DDQ supply.
6. I_OHJ = –4 mA
7. I_OLJ = + 4 mA
8. I_OHJC = –100 uA
9. I_OHJC = +100 uA
JTAG Port Timing Diagram
TCK
TDI
TMS
TDO
Parallel SRAM input
tTKC
tTKH
tTH
tTS
tTH
tTS
tTKQ
tTH
tTS
tTKL
Rev: 2.04 5/2005
24/27
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2002, GSI Technology, Inc.