GS8170DW36C Datasheet, PDF (18/27 Pages) GSI Technology – 18Mb Σ1x1Dp CMOS I/O Double Late Write SigmaRAM

CK
A
E2
DQ(Data Out)
CQ
GS8170DW36/72C-333/300/250/200
Timing Parameter Key—Pipelined Read Cycle Timing
KHKL
KLKH
KHKH
AVKH
A
KHAX
B
KHCH
KLCL
KHQV
KHQX1
Q(A)
CHQV
KHQZ
KHQX
Q(B)
CHQX
KHCX1
KHCZ
Timing Parameter Key—Double Late Write Mode Control and Data In Timing
CK
tAVKH
tKHAX
A
A
B
C
E1, E2, E3,
W, Bx, ADV
tnVKH
tKHnX
DQ (Data In)
tDVKH
DA
tKHDX
Note: tnVKH = tEVKH, tWVKH, tBVKH, etc. and tKHnX = tKHEX, tKHWX, tKHBX, etc.
Rev: 2.04 5/2005
18/27
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2002, GSI Technology, Inc.