GS816218B Datasheet, PDF (8/41 Pages) GSI Technology – 1M x 18, 512K x 36, 256K x 72 18Mb Sync Burst SRAMs

GS816218(B/D)/GS816236(B/D)/GS816272(C)
GS816218/36 BGA Pin Description
Symbol
A0, A1
An
DQA
DQB
DQC
DQD
BA, BB, BC, BD
NC
CK
BW
GW
E1
G
ADV
ADSP, ADSC
ZZ
FT
LBO
ZQ
SCD
TMS
TDI
TDO
TCK
PE
V_DD
V_SS
V_DDQ
Type
I
I
Description
Address field LSBs and Address Counter Preset Inputs
Address Inputs
I/O
Data Input and Output pins
I
Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low
—
No Connect
I
Clock Input Signal; active high
I
Byte Write—Writes all enabled bytes; active low
I
Global Write Enable—Writes all bytes; active low
I
Chip Enable; active low
I
Output Enable; active low
I
Burst address counter advance enable; active low
I
Address Strobe (Processor, Cache Controller); active low
I
Sleep mode control; active high
I
Flow Through or Pipeline mode; active low
I
Linear Burst Order mode; active low
I
FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low
Drive])
I
Single Cycle Deselect/Dual Cyle Deselect Mode Control
I
Scan Test Mode Select
I
Scan Test Data In
O
Scan Test Data Out
I
Scan Test Clock
I
Parity Bit Enable; active low
I
Core power supply
I
I/O and Core Ground
I
Output driver power supply
Rev: 2.17 11/2004
8/41
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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