GS816218B Datasheet, PDF (3/41 Pages) GSI Technology – 1M x 18, 512K x 36, 256K x 72 18Mb Sync Burst SRAMs

GS816272 BGA Pin Description
Symbol
A0, A1
An
DQA
DQB
DQC
DQD
DQE
DQF
DQG
DQH
Type
I
I
I/O
BA, BB, BC,BD, BE, BF, BG,BH
I
NC
—
CK
I
GW
I
E1, E3
I
E2
I
G
I
ADV
I
ADSP, ADSC
I
ZZ
I
FT
I
LBO
I
SCD
I
MCH
I
MCL
BW
I
ZQ
I
TMS
I
TDI
I
TDO
O
TCK
I
V_DD
I
V_SS
I
V_DDQ
I
GS816218(B/D)/GS816236(B/D)/GS816272(C)
Description
Address field LSBs and Address Counter Preset Inputs.
Address Inputs
Data Input and Output pins
Byte Write Enable for DQA, DQB, DQC, DQD, DQE,
DQF, DQG, DQH I/Os; active low
No Connect
Clock Input Signal; active high
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
Chip Enable; active high
Output Enable; active low
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Sleep Mode control; active high
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Single Cycle Deselect/Dual Cycle Deselect Mode Control
Must Connect High
Must Connect Low
Byte Enable; active low
FLXDrive Output Impedance Control
(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])
Scan Test Mode Select
Scan Test Data In
Scan Test Data Out
Scan Test Clock
Core power supply
I/O and Core Ground
Output driver power supply
Rev: 2.17 11/2004
3/41
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology