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GS72108TP-10 Datasheet, PDF (7/12 Pages) GSI Technology – 256K x 8 2Mb Asynchronous SRAM
Read Cycle 2: WE = VIH
Address
CE
OE
Data Out
tRC
tAA
tAC
tLZ
tOE
tOLZ
High impedance
tHZ
tOHZ
DATA VALID
GS72108TP/J
Write Cycle
Parameter
Write cycle time
Address valid to end of write
Chip enable to end of write
Data set up time
Data hold time
Write pulse width
Address set up time
Write recovery time (WE)
Write recovery time (CE)
Output Low Z from end of write
Write to output in High Z
-8
-10
-12
-15
Symbol
Unit
Min Max Min Max Min Max Min Max
tWC
8 — 10 — 12 — 15 — ns
tAW
5.5 — 7
— 8 — 10 — ns
tCW
5.5 — 7
— 8 — 10 — ns
tDW
4 — 5 — 6 — 7 — ns
tDH
0 — 0 — 0 — 0 — ns
tWP
5.5 — 7
— 8 — 10 — ns
tAS
0 — 0 — 0 — 0 — ns
tWR
0 — 0 — 0 — 0 — ns
tWR1
0 — 0 — 0 — 0 — ns
tWLZ*
3—
3
—
3
— 3 — ns
tWHZ* — 3.5 —
4
—
5
—
6
ns
* These parameters are sampled and are not 100% tested.
Rev: 1.08 7/2002
7/12
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.