GS8321E18E-V Datasheet, PDF (6/31 Pages) GSI Technology – 2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs

GS8321E18/32/36E-xxxV Block Diagram
GS8321E18/32/36E-xxxV
A0–An
LBO
ADV
CK
ADSC
ADSP
GW
BW
BA
BB
BC
BD
Register
DQ
A0
A1
A0
D0
Q0 _A1
D1
Q1
Counter
Load
Register
DQ
Register
DQ
Register
DQ
Register
DQ
Register
DQ
Register
E1
DQ
Register
DQ
FT
G
Power Down
0
ZZ
Control
Note: Only x36 version shown for simplicity.
A
Memory
Array
Q
36
D
36
4
4
36
36
36
DQx1–DQx9
36
36
4
32
Parity
Encode
4
Parity
Compare
NC
NC
Rev: 1.04 6/2006
6/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology