GS8321E18E-V Datasheet, PDF(5/31 Page) GSI Technology – 2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs

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GS8321E18E-V Datasheet, PDF (5/31 Pages) GSI Technology – 2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs

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GS8321E18/32/36E-xxxV

GS8321E18/32/36E-xxxV 165-Bump BGA Pin Description

Symbol

A0, A1

A

DQA

DQB

DQC

DQD

BA, BB, BC, BD

NC

CK

BW

GW

E1

E3

E2

G

ADV

ADSC, ADSP

ZZ

FT

LBO

TMS

TDI

TDO

TCK

MCL

VDD

VSS

VDDQ

Type

I

I

I/O

I

â

I

I

I

I

I

I

I

I

I

I

I

I

I

I

O

I

â

I

I

I

Description

Address field LSBs and Address Counter Preset Inputs

Address Inputs

Data Input and Output pins

Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low

No Connect

Clock Input Signal; active high

Byte WriteâWrites all enabled bytes; active low

Global Write EnableâWrites all bytes; active low

Chip Enable; active low

Chip Enable; active low

Chip Enable; active high

Output Enable; active low

Burst address counter advance enable; active l0w

Address Strobe (Processor, Cache Controller); active low

Sleep mode control; active high

Flow Through or Pipeline mode; active low

Linear Burst Order mode; active low

Scan Test Mode Select

Scan Test Data In

Scan Test Data Out

Scan Test Clock

Must Connect Low

Core power supply

I/O and Core Ground

Output driver power supply

Rev: 1.04 6/2006

5/31

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Â© 2003, GSI Technology

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