GS8321E18E-V Datasheet, PDF (14/31 Pages) GSI Technology – 2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs

GS8321E18/32/36E-xxxV
AC Test Conditions
Parameter
Conditions
Input high level
V_DD – 0.2 V
Input low level
0.2 V
Input slew rate
1 V/ns
Input reference level
V_DD/2
Output reference level
V_DDQ/2
Output load
Fig. 1
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.
3. Device is deselected as defined by the Truth Table.
Figure 1
Output Load 1
DQ
50Ω
30pF^*
V_DDQ/2
* Distributed Test Jig Capacitance
DC Electrical Characteristics
Parameter
Input Leakage Current
(except mode pins)
FT, ZZ Input Current
Output Leakage Current
Symbol
I_IL
I_IN
I_OL
Test Conditions
V_IN = 0 to V_DD
V_DD ≥ V_IN ≥ 0 V
Output Disable, V_OUT = 0 to V_DD
Min
–1 uA
–100 uA
–1 uA
Max
1 uA
100 uA
1 uA
DC Output Characteristics (1.8 V/2.5 V Version)
Parameter
1.8 V Output High Voltage
2.5 V Output High Voltage
1.8 V Output Low Voltage
2.5 V Output Low Voltage
Symbol
V_OH1
V_OH2
V_OL1
V_OL2
Test Conditions
I_OH = –4 mA, V_DDQ = 1.6 V
I_OH = –8 mA, V_DDQ = 2.375 V
I_OL = 4 mA
I_OL = 8 mA
Min
Max
V_DDQ – 0.4 V
—
1.7 V
—
—
0.4 V
—
0.4 V
Rev: 1.04 6/2006
14/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology