GS8162Z18BB-V Datasheet, PDF(6/33 Page) GSI Technology – 18Mb Pipelined and Flow Through Synchronous NBT SRAM

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

GS8162Z18BB-V Datasheet, PDF (6/33 Pages) GSI Technology – 18Mb Pipelined and Flow Through Synchronous NBT SRAM

◁

Preliminary

GS8162ZxxB(B/D)-xxxV

GS8162Z18/36-xxxV 119-Bump and 165-Bump BGA Pin Description

Symbol

A0, A1

A

DQA

DQB

DQC

DQD

BA, BB, BC, BD

NC

CK

CKE

W

E1

E3

E2

G

ADV

ZZ

FT

LBO

ZQ

TMS

TDI

TDO

TCK

VDD

VSS

VDDQ

Type

I

I

Description

Address field LSBs and Address Counter Preset Inputs

Address Inputs

I/O

Data Input and Output pins

I

Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low

â

No Connect

I

Clock Input Signal; active high

I

Clock Enable; active low

I

Write Enable; active low

I

Chip Enable; active low

I

Chip Enable; active low

I

Chip Enable; active high

I

Output Enable; active low

I

Burst address counter advance enable; active high

I

Sleep mode control; active high

I

Flow Through or Pipeline mode; active low

I

Linear Burst Order mode; active low

I

FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low

Drive])

I

Scan Test Mode Select

I

Scan Test Data In

O

Scan Test Data Out

I

Scan Test Clock

I

Core power supply

I

I/O and Core Ground

I

Output driver power supply

BPR1999.05.18

Rev: 1.01a 6/2006

6/33

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Â© 2004, GSI Technology

▷