GS8162Z18BB-V Datasheet, PDF (1/33 Pages) GSI Technology – 18Mb Pipelined and Flow Through Synchronous NBT SRAM

Preliminary
GS8162ZxxB(B/D)-xxxV
119- & 165-Bump BGA
Commercial Temp
Industrial Temp
18Mb Pipelined and Flow Through
Synchronous NBT SRAM
250 MHz–150 MHz
1.8 V or 2.5 V V_DD
1.8 V or 2.5 V I/O
Features
• NBT (No Bus Turn Around) functionality allows zero wait
Read-Write-Read bus utilization; fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs
• 1.8 V or 2.5 V core power supply
• 1.8 V or 2.5 V I/O supply
• User-configurable Pipeline and Flow Through mode
• ZQ mode pin for user-selectable high/low output drive
• IEEE 1149.1 JTAG-compatible Boundary Scan
• On-chip write parity checking; even or odd selectable
• On-chip parity encoding and error detection
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2M, 4M, and 8M devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 119- and 165-bump BGA packages
• RoHS-compliant 119- and 165-bump BGA packages
available
Functional Description
The GS8162ZxxB(B/D)-xxxV is an 18Mbit Synchronous
Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL
or other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8162ZxxB(B/D)-xxxV may be configured by the user
to operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge-
triggered registers that capture input signals, the device
incorporates a rising edge triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge-triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS8162ZxxB(B/D)-xxxV is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 119-bump or 165-bump BGA package.
Pipeline
3-1-1-1
Flow Through
2-1-1-1
Parameter Synopsis
-250 -200 -150 Unit
t_KQ
tCycle
3.0
3.0
3.8
ns
4.0
5.0
6.7
ns
Curr (x18)
Curr (x32/x36)
280
230
185
mA
330
270
210
mA
t_KQ
tCycle
5.5
6.5
7.5
ns
5.5
6.5
7.5
ns
Curr (x18)
Curr (x32/x36)
210
185
170
mA
240
205
190
mA
Rev: 1.01a 6/2006
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology