GS78116AB Datasheet, PDF (6/11 Pages) GSI Technology – 512K x 16 8Mb Asynchronous SRAM

Address
Data Out
Read Cycle 1:CE = OE = VIL
t_RC
t_AA
t_OH
Previous Data
Data valid
GS78116AB
* These parameters are sampled and are not 100% tested
Write Cycle
Parameter
Write cycle time
Address valid to end of write
Chip enable to end of write
Data set up time
Data hold time
Write pulse width
Address set up time
Write recovery time (WE)
Write recovery time (CE)
Output Low Z from end of write
Write to output in High Z
-8
-10
-12
Symbol
Unit
Min Max Min Max Min Max
tWC
8
—
10
—
12
—
ns
tAW
5.5
—
7
—
8
—
ns
tCW
5.5
—
7
—
8
—
ns
tDW
4
—
5
—
6
—
ns
tDH
0
—
0
—
0
—
ns
tWP
5.5
—
7
—
8
—
ns
tAS
0
—
0
—
0
—
ns
tWR
0
—
0
—
0
—
ns
tWR1
0
—
0
—
0
—
ns
tWLZ^*
3
—
3
—
3
—
ns
tWHZ^*
—
3.5
—
4
—
5
ns
Rev: 1.04 5/2006
6/11
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology