GS8160E18T Datasheet, PDF (5/25 Pages) GSI Technology – 1M x 18, 512K x 36 18Mb Sync Burst SRAMs

TQFP Pin Description
Symbol
A0, A1
A
DQA
DQB
DQC
DQD
NC
BW
BA, BB, BC, BD
CK
GW
E1
E2
E3
G
ADV
ADSP, ADSC
ZZ
LBO
V_DD
V_SS
V_DDQ
Type
I
I
I/O
—
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
GS8160E18/32/36T-250/225/200/166/150/133
Description
Address field LSBs and Address Counter preset Inputs
Address Input
Data Input and Output pins
No Connect
Byte Write—Writes all enabled bytes; active low
Byte Write Enable for DQA, DQB Data I/Os; active low
Clock Input Signal; active high
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
Chip Enable; active high
Chip Enable; active low
Output Enable; active low
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Sleep Mode control; active high
Linear Burst Order mode; active low
Core power supply
I/O and Core Ground
Output driver power supply
Rev: 2.13 11/2004
5/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology