GS8160E18T Datasheet, PDF (1/25 Pages) GSI Technology – 1M x 18, 512K x 36 18Mb Sync Burst SRAMs

GS8160E18/32/36T-250/225/200/166/150/133
100-Pin TQFP
Commercial Temp
Industrial Temp
1M x 18, 512K x 36
18Mb Sync Burst SRAMs
250 MHz–133 MHz
2.5 V or 3.3 V V_DD
2.5 V or 3.3 V I/O
Features
• FT pin for user-configurable flow through or pipeline
operation
• Dual Cycle Deselect (DCD) operation
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP package
Functional Description
Applications
The GS8160E18/32/36T is an 18,874,368-bit (16,777,216-bit for x32
version) high performance synchronous SRAM with a 2-bit burst
address counter. Although of a type originally developed for Level 2
Cache applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications, ranging
from DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst control
inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW)
are synchronous and are controlled by a positive-edge-triggered clock
input (CK). Output enable (G) and power down control (ZZ) are
asynchronous inputs. Burst cycles can be initiated with either ADSP
or ADSC inputs. In Burst mode, subsequent burst addresses are
generated internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or interleave order
with the Linear Burst Order (LBO) input. The Burst function need not
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the user
via the FT mode pin (Pin 14). Holding the FT mode pin low places the
RAM in Flow Through mode, causing output data to bypass the Data
Output Register. Holding FT high places the RAM in Pipeline mode,
activating the rising-edge-triggered Data Output Register.
DCD Pipelined Reads
The GS8160E18/32/36T is a DCD (Dual Cycle Deselect) pipelined
synchronous SRAM. SCD (Single Cycle Deselect) versions are also
available. DCD SRAMs pipeline disable commands to the same
degree as read commands. DCD RAMs hold the deselect command
for one full cycle and then begin turning off their outputs just after the
second rising edge of clock.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable (BW)
input combined with one or more individual byte write signals (Bx).
In addition, Global Write (GW) is available for writing all bytes at one
time, regardless of the Byte Write control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High) of
the ZZ signal, or by stopping the clock (CK). Memory data is retained
during Sleep mode.
Core and Interface Voltages
The GS8160E18/32/36T operates on a 2.5 V or 3.3 V power supply.
All input are 3.3 V and 2.5 V compatible. Separate output power
(V_DDQ) pins are used to decouple output noise from the internal
circuits and are 3.3 V and 2.5 V compatible.
Parameter Synopsis
Pipeline
3-1-1-1
3.3 V
2.5 V
Flow
Through
2-1-1-1
3.3 V
2.5 V
-250 -225 -200 -166 -150 -133 Unit
t_KQ
tCycle
2.5 2.7 3.0 3.4 3.8 4.0 ns
4.0 4.4 5.0 6.0 6.7 7.5 ns
Curr (x18) 280 255 230 200 185 165 mA
Curr (x32/x36) 330 300 270 230 215 190 mA
Curr (x18) 275 250 230 195 180 165 mA
Curr (x32/x36) 320 295 265 225 210 185 mA
t_KQ
tCycle
5.5 6.0 6.5 7.0 7.5 8.5 ns
5.5 6.0 6.5 7.0 7.5 8.5 ns
Curr (x18) 175 165 160 150 145 135 mA
Curr (x32/x36) 200 190 180 170 165 150 mA
Curr (x18) 175 165 160 150 145 135 mA
Curr (x32/x36) 200 190 180 170 165 150 mA
Rev: 2.13 11/2004
1/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology