GS8160E18T Datasheet, PDF (11/25 Pages) GSI Technology – 1M x 18, 512K x 36 18Mb Sync Burst SRAMs

GS8160E18/32/36T-250/225/200/166/150/133
Simplified State Diagram with G
X
Deselect
W
R
W
R
X
First Write ^R
CW
CR
W
First Read ^X
CW
CR
W
X
R
Burst Write
CR
CW
R
W
Burst Read ^X
CW
CR
Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.
3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
Rev: 2.13 11/2004
11/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology