GS816273C Datasheet, PDF (4/25 Pages) GSI Technology – 256K x 72 18Mb S/DCD Sync Burst SRAMs

GS816273C-250/225
Mode Pin Functions
Mode Name
Pin
Name
State
Function
Burst Order Control
L
LBO
H
Linear Burst
Interleaved Burst
Power Down Control
Single/Dual Cycle Deselect Control
L or NC
ZZ
H
L
SCD
H or NC
Active
Standby, I_DD = I_SB
Dual Cycle Deselect
Single Cycle Deselect
L
High Drive (Low Impedance)
FLXDrive Output Impedance Control ZQ
H or NC Low Drive (High Impedance)
9th Bit Enable
L
Activate DQPx I/Os (x18/x36
mode)
PE
H or NC
Deactivate DQPx I/Os (x16/x32
mode)
Note:
There is a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as specified in the
above tables.
Burst Counter Sequences
Linear Burst Sequence
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
Note:
The burst counter wraps to initial state on the 5th clock.
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00
Note:
The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Rev: 1.03 7/2004
4/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2002, GSI Technology