GS816273C Datasheet, PDF (3/25 Pages) GSI Technology – 256K x 72 18Mb S/DCD Sync Burst SRAMs

GS816273C-250/225
GS816273 BGA Pin Description
Symbol
A0, A1
A
DQA
DQB
DQC
DQD
DQE
DQF
DQG
DQH
BA, BB, BC,BD, BE, BF,
BG,BH
NC
CK
GW
E1, E3
E2
G
ADV
ADSP, ADSC
ZZ
LBO
SCD
MCH
MCL
BW
Type
I
I
I/O
I
—
I
I
I
I
I
I
I
I
I
I
I
I
ZQ
I
TMS
I
TDI
I
TDO
O
TCK
I
V_DD
I
V_SS
I
V_DDQ
I
V_DDQ/DNU
—
Description
Address field LSBs and Address Counter Preset Inputs.
Address Inputs
Data Input and Output pins
Byte Write Enable for DQA, DQB, DQC, DQD, DQE,
DQF, DQG, DQH I/Os; active low
No Connect
Clock Input Signal; active high
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
Chip Enable; active high
Output Enable; active low
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Sleep Mode control; active high
Linear Burst Order mode; active low
Single Cycle Deselect/Dual Cycle Deselect Mode Control
Must Connect High
Must Connect Low
Byte Enable; active low
FLXDrive Output Impedance Control
(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])
Scan Test Mode Select
Scan Test Data In
Scan Test Data Out
Scan Test Clock
Core power supply
I/O and Core Ground
Output driver power supply
V_DDQ or V_DD (must be tied high)
or
Do Not Use (must be left floating)
Rev: 1.03 7/2004
3/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2002, GSI Technology