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GS815018AB Datasheet, PDF (4/25 Pages) GSI Technology – 1M x 18, 512K x 36 18Mb Register-Register Late Write SRAM
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GS815018/36AB-357/333/300/250
GS815018/36 BGA Pin Description
Symbol
A
DQA
DQB
DQC
DQD
BA, BB, BC, BD
NC
CK
CK
SW
G
ZZ
M1
M2
ZQ
SS
TMS
TDI
TDO
TCK
VREF
VDD
VSS
VDDQ
Type
I
Description
Address Inputs
I/O
Data Input and Output pins
I
Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low
—
No Connect
I
Clock Input Signal; active high
I
Clock Input Signal; active low
I
Write Enable; active low
I
Output Enable; active low
I
Sleep mode control; active high
I
Read Operation Protocol Select—Selects Register-Register read operations; must be tied low in this
device
I
Read Operation Protocol Select—Selects Register-Register read operations; must be tied high in this
device
I
FLXDrive-II™ Output Impedance Control
I
Synchronous Select Input
I
Scan Test Mode Select
I
Scan Test Data In
O
Scan Test Data Out
I
Scan Test Clock
I
Input Reference Voltage
I
Core power supply
I
I/O and Core Ground
I
Output driver power supply
Read Operations
Pipelined Read
A read cycle begins when the RAM captures logic 0 on SS and logic 1 on SW at the rising edge of K (and the falling edge of K).
Address inputs captured on that clock edge are propigated into the RAM, which delivers data to the input of the output registers.
The second rising edge of K fires the output registers and releases read data to the output drivers. If G is held active low, the
drivers drive the data onto the output pins. Read data is sustained on the output pins as long as G is held low or until the next rising
edge of K, at which point the outputs may update to new data or deselect, depending on what control command was registered at
the second rising edge of K.
Dual Cycle Deselect
Chip deselect (SS = logic 1) is pipelined to the same degree as read data. Therefore, a deselect command entered on the rising edge
of K is acted upon in response to the next rising edge of K.
Rev: 1.05 10/2005
4/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology