GS8162ZV72CC Datasheet, PDF (3/27 Pages) GSI Technology – 18Mb Pipelined and Flow Through Synchronous NBT SRAM

GS8162ZV72 BGA Pin Description
Symbol
A0, A1
A
DQA
DQB
DQC
DQD
DQE
DQF
DQG
DQH
BA, BB, BC,BD, BE, BF,
BG,BH
NC
CK
W
E1, E3
E2
G
ADV
ZZ
FT
LBO
MCH
MCL
CKE
BW
Type
I
I
I/O
I
—
I
I
I
I
I
I
I
I
I
I
I
I
ZQ
I
TMS
I
TDI
I
TDO
O
TCK
I
V_DD
I
V_SS
I
V_DDQ
I
Preliminary
GS8162ZV72CC-333/300/250/200/150
Description
Address field LSBs and Address Counter Preset Inputs
Address Inputs
Data Input and Output pins
Byte Write Enable for DQA, DQB, DQC, DQD, DQE,
DQF, DQG, DQH I/Os; active low
No Connect
Clock Input Signal; active high
Write Enable. Writes all enabled bytes; active low
Chip Enable; active low
Chip Enable; active high
Output Enable; active low
Burst address counter advance enable; active high
Sleep Mode control; active high
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Must Connect High
Must Connect Low
Clock Enable; active low
Byte Enable; active low
FLXDrive Output Impedance Control
(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])
Scan Test Mode Select
Scan Test Data In
Scan Test Data Out
Scan Test Clock
Core power supply
I/O and Core Ground
Output driver power supply
Rev: 1.01a 2/2006
3/27
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology