GS8162ZV72CC Datasheet, PDF (21/27 Pages) GSI Technology – 18Mb Pipelined and Flow Through Synchronous NBT SRAM

Preliminary
GS8162ZV72CC-333/300/250/200/150
JTAG Tap Controller State Diagram
Test Logic Reset
1
0
Run Test Idle ¹
0
Select DR ¹
0
1 _{Capture DR}
0
Select IR ¹
0
1 _{Capture IR}
0
Shift DR
1
0
1
Exit1 DR
0
Shift IR
1
0
1
Exit1 IR
0
Pause DR
1
0
Pause IR
1
0
Exit2 DR ₀
1
Exit2 IR
0
1
Update DR
1
0
Update IR
1
0
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This
occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate
testing of other devices in the scan path.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded
in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers
into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded
with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM
clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the
input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the
device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data
capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP operation except cap-
turing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then places the boundary
scan register between the TDI and TDO pins.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all
logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is still
Rev: 1.01a 2/2006
21/27
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology