GS8180DV18D Datasheet, PDF (25/28 Pages) GSI Technology – 18Mb Burst of 4 SigmaQuad SRAM

GS8180DV18D-250/200/167/133/100
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter
Symbol
Min.
Max.
Unit Notes
Test Port Input High Voltage
Test Port Input Low Voltage
V_IHJ
0.6 * V_DD
V_DD2 +0.3
V
1
V_ILJ
–0.3
0.3 * V_DD
V
1
TMS, TCK and TDI Input Leakage Current
TMS, TCK and TDI Input Leakage Current
TDO Output Leakage Current
Test Port Output High Voltage
Test Port Output Low Voltage
I_INHJ
I_INLJ
I_OLJ
V_OHJ
V_OLJ
–300
–1
–1
1.7
—
1
uA
2
100
uA
3
1
uA
4
—
V 5, 6
0.4
V 5, 7
Test Port Output CMOS High
V_OHJC V_DDQ – 100 mV
—
V 5, 8
Test Port Output CMOS Low
V_OLJC
—
100 mV
V 5, 9
Notes:
1. Input Under/overshoot voltage must be – V > Vi < V_DDn + V not to exceed .6 V maximum, with a pulse width not to exceed 20% tTKC.
2. V_ILJ ≤ V_IN ≤ V_DDn
3. 0 V ≤ V_IN ≤ V_ILJn
4. Output Disable, V_OUT = 0 to V_DDn
5. The TDO output driver is served by the V_DDQ supply.
6. I_OHJ = –4 mA
7. I_OLJ = + 4 mA
8. I_OHJC = –100 uA
9. I_OLJC = +100 uA
JTAG Port Timing Diagram
TCK
TDI
TMS
TDO
Parallel SRAM input
tTKC
tTKH
tTH
tTS
tTH
tTS
tTKQ
tTH
tTS
tTKL
Rev: 2.04 4/2005
25/28
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2002, GSI Technology