GS8180DV18D Datasheet, PDF (10/28 Pages) GSI Technology – 18Mb Burst of 4 SigmaQuad SRAM

GS8180DV18D-250/200/167/133/100
Byte Write Clock Truth Table
BW BW BW BW
Current Operation
D
D
D
D
K↑
K↑
K↑
K↑
K↑
K↑
K↑
K↑
K↑
(t_n+1) (t_n+1½) (t_n+2) (t_n+2½)
(t_n)
(t_n+1) (t_n+1½) (t_n+2) (t_n+2½)
T
T
T
T
Write
Dx stored if BWn = 0 in all four data transfers
D0
D2
D3
D4
T
F
F
F
Write
Dx stored if BWn = 0 in 1st data transfer only
D0
X
X
X
F
T
F
F
Write
Dx stored if BWn = 0 in 2nd data transfer only
X
D1
X
X
F
F
T
F
Write
Dx stored if BWn = 0 in 3rd data transfer only
X
X
D2
X
F
F
F
T
Write
Dx stored if BWn = 0 in 4th data transfer only
X
X
X
D3
F
F
F
F
Write Abort
No Dx stored in any of the four data transfers
X
X
X
X
Notes:
1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
2. If one or more BWn = 0, then BW = “T”, else BW = “F”.
x18 Byte Write Enable (BWn) Truth Table
BW0 BW1
1
1
0
1
1
0
0
0
D0–D8
Don’t Care
Data In
Don’t Care
Data In
D9–D17
Don’t Care
Don’t Care
Data In
Data In
Rev: 2.04 4/2005
10/28
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2002, GSI Technology