GS8180DV18D Datasheet, PDF (15/28 Pages) GSI Technology – 18Mb Burst of 4 SigmaQuad SRAM

GS8180DV18D-250/200/167/133/100
Input and Output Leakage Characteristics
Parameter
Input Leakage Current
(except mode pins)
Symbol
I_IL
Output Leakage Current
I_OL
Test Conditions
V_IN = 0 to V_DD
Output Disable,
V_OUT = 0 to V_DDQ
Min.
–2 uA
–2 uA
Max Notes
2 uA
2 uA
Programmable Impedance HSTL Output Driver DC Electrical Characteristics
Parameter
Symbol
Min.
Output High Voltage
V_OH1
V_DDQ/2
Output Low Voltage
V_OL1
Vss
Output High Voltage
V_OH2
V_DDQ – 0.2
Output Low Voltage
V_OL2
Vss
Notes:
1. I_OH = (V_DDQ/2) / (RQ/5) +/– 15% @ V_OH = V_DDQ/2 (for: 175Ω ≤ RQ ≤ 350Ω).
2. I_OL = (V_DDQ/2) / (RQ/5) +/– 15% @ V_OL = V_DDQ/2 (for: 175Ω ≤ RQ ≤ 350Ω).
3. Parameter tested with RQ = 250Ω and V_DDQ = 1.5 V or 1.8 V
4. Minimum Impedance mode, ZQ = V_SS
5. I_OH = –1.0 mA
6. I_OL = 1.0 mA
Max.
V_DDQ
V_DDQ/2
V_DDQ
0.2
Units Notes
V
1, 3
V
2, 3
V
4, 5
V
4, 6
Operating Currents
-250
-200
-167
-133
-100
Parameter Org Symbol _{0°C –40°C 0°C –40°C 0°C –40°C 0°C –40°C 0°C –40°C}
to
to
to
to
to
to
to
to
to
to
70°C +85°C 70°C +85°C 70°C +85°C 70°C +85°C 70°C +85°C
Operating
Current
x18
IDD
TBD TBD
460
mA
TBD
400
mA
TBD
340
mA
TBD
280
mA
TBD
IDDQ TBD TBD 95 mA TBD 85 mA TBD 70 mA TBD 65 mA TBD
Test Conditions
R and W ≤ V_IL Max.
tKHKH ≥ tKHKH Min.
All other inputs
V_IN ≤ V_IL Max. or V_IN ≥ V_IH Min.
Chip
Disable
Current
ISB1 TBD
x18
ISBQ1 TBD
TBD
130
mA
TBD
120
mA
TBD
115
mA
TBD
110
mA
TBD
TBD 5 mA TBD 5 mA TBD 5 mA TBD 5 mA TBD
Note:
Power measured with output pins floating.
R and W ≥ V_IH Min.
tKHKH ≥ tKHKH Min.
All other inputs
V_IN ≤ V_IL Max. or V_IN ≥ V_IH Min.
Rev: 2.04 4/2005
15/28
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2002, GSI Technology