GS84118T-166 Datasheet, PDF (24/30 Pages) GSI Technology – 256K x 18 Sync Cache Tag

GS84118T/B-166/150/130/100
Instruction Register (3 Bits)
The JTAG Instruction register is consisted of shift register stage and parallel output latch. The register is 3 bits wide and is encoded
as follow:
Octal MSB — LSB
0
0
0
0
1
0
0
1
2
0
1
0
3
0
1
1
4
1
0
0
5
1
0
1
6
1
1
0
7
1
1
1
Instruction
Bypass
IDCODE—Read device ID
Sample-Z—Sample Inputs and tri-state DQs, Match
Bypass
Sample—Sample Inputs
Private—Manufacturer use only
Bypass
Bypass
Bypass Register (1 Bit)
The Bypass Register is one bit wide and is connected electrically between TDI and TDO and provides the minimum length serially
path between TDI and TDO.
ID Register (32 Bits)
The ID Register are 32 bits wide and are listed as follow:
Header
GSI ID
(89 decimal in bank 2)
Part Number
Revision Number
ID[0]
ID[7:1]
ID[11:8]
ID[27:12]
ID[31:28]
1
101 1001
0001
0000 0000 0000 0000
xxxx
Rev: 1.05 7/2001
24/30
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.