GS84118T-166 Datasheet, PDF (1/30 Pages) GSI Technology – 256K x 18 Sync Cache Tag

TQFP, BGA
Commercial Temp
Industrial Temp
256K x 18 Sync
Cache Tag
GS84118T/B-166/150/133/100
166 MHz–100 MHz
8.5 ns–12 ns
3.3 V V_DD
3.3 V and 2.5 V I/O
Features
• 3.3 V +10%/–5% core power supply, 2.5 V or 3.3 V I/O
supply
• Intergrated data comparator for Tag RAM application
• FT mode pin for flow through or pipeline operation
• LBO pin for Linear or Interleave (Pentium^TM and X86) Burst
mode
• Synchronous address, data I/O, and control inputs
• Synchronous Data Enable (DE)
• Asynchronous Output Enable (OE)
• Asynchronous Match Output Enable (MOE)
• Byte Write (BWE) and Global Write (GW) operation
• Three chip enable signals for easy depth expansion
• Internal self-timed write cycle
• JTAG Test mode conforms to IEEE standard 1149.1
• JEDEC-standard 100-lead TQFP package and 119-BGA:
T:TQFP or B: BGA
Pipeline
3-1-1-1
Flow
Through
2-1-1-1
-166
-150
-133
-100
t_{cycle 6.0 ns 6.6 ns 7.5 ns 10 ns}
t_KQ 3.5 ns 3.8 ns 4.0 ns 4.5 ns
I_DD 310 mA 275 mA 250 mA 190 mA
t_{KQ 8.5 ns 10 ns 11 ns 12 ns}
t_cycle 10 ns 10 ns 15 ns 15 ns
I_DD 190 mA 190 mA 140 mA 140 mA
Functional Description
The GS84118 is a 256K x 18 high performance synchronous
SRAM with integrated Tag RAM comparator. A 2-bit burst
counter is included to provide burst interface with Pentium^TM
and other high performance CPUs. It is designed to be used as
a Cache Tag SRAM, as well as data SRAM. Addresses, data
IOs, match output, chip enables (CE1, CE2, CE3), address
control inputs (ADSP, ADSC, ADV), and write control inputs
(BW1, BW2, BWE, GW, DE) are synchronous and are
controlled by a positive-edge-triggered clock (CLK).
Output registers and the Match output register are provided and
controlled by the FT mode pin (Pin 14). Through use of the FT
mode pin, I/O registers can be programmed to perform pipeline
or flow through operation. Flow Through mode reduces
latency.
Byte write operation is performed by using Byte Write Enable
(BWE) input combined with two individual byte write signals
BW1-2. In addition, Global Write (GW) is available for
writing all bytes at one time.
Compare cycles begin as a read cycle with output disabled so
that compare data can be loaded into the data input register.
The comparator compares the read data with the registered
input data and a match signal is generated. The match output
can be either in Pipeline or Flow Through modes controlled by
the FT signal.
Low power (Standby mode) is attained through the assertion of
the ZZ signal, or by stopping the clock (CLK). Memory data is
retained during Standby mode.
JTAG boundary scan interface is provided using IEEE
standard 1149.1 protocol. Four pins—Test Data In (TDI), Test
Data Out (TDO), Test Clock (TCK) and Test Mode Select
(TMS)—are used to perform JTAG function.
The GS84118 operates on a 3.3 V power supply and all inputs/
outputs are 3.3 V- or 2.5 V-LVTTL-compatible. Separate
output (V_DDQ) pins are used to allow both 3.3 V or 2.5 V IO
interface.
* Pentium is a trademark of Intel Corp.
Output Enable (OE), Match Output Enable, and power down
control (ZZ) are asynchronous. Burst can be initiated with
either ADSP or ADSC inputs. Subsequent burst addresses are
generated internally and are controlled by ADV. The burst
sequence is either interleave order (Pentium^TM or x86) or
linear order, and is controlled by LBO.
Rev: 1.05 7/2001
1/30
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Trademark Notice (if any) Trademark of Giga Semiconductor, Inc. (GSI Technology).
© 1999, Giga Semiconductor, Inc.