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| GS84118T-166 Datasheet, PDF (15/30 Pages) GSI Technology – 256K x 18 Sync Cache Tag | |||
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Write Cycle Timing
GS84118T/B-166/150/130/100
CLK
ADSP
ADSC
ADV
A0âA17
GW
BWE
BW1â
BW2
CE1
CE2
CE3
Single Write
Burst Write
Write
Deselected
tS tH
tS tH
tKH tKL tKC ADSP is blocked by CE1 inactive
ADSC initiated write
tS tH
tS tH ADV must be inactive for ADSP Write
WR1
WR2
WR3
tS tH
tS tH
tS tH
WWRR11
tS tH
tS tH
WWRR22
CE1 masks ADSP
WWRR33
Deselected with CE2
tS tH
CE2 and CE3 only sampled with ADSP or ADSC
OE
DQ1â16 Hi-Z
DQP1â2
DE
tS tH
D1a
tS tH
Write specified byte for 2a and all bytes for 2b, 2c& 2d
D2a
D2b
D2c
D2d
D3a
Rev: 1.05 7/2001
15/30
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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