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| GS8170DD36C Datasheet, PDF (20/29 Pages) GSI Technology – 18Mb Σ1x2Lp CMOS I/O Double Data Rate SigmaRAM | |||
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GS8170DD36C-333/300/250/200
Timing Parameter KeyâDDR Control and Data In Timing
CK
tAVKH
tKHAX
A
A
B
C
tnVKH
tKHnX
E1, E2, E3,
W, ADV
tDVKH
tKHDX
DQ (Data In)
DDR Write
DA1
DA2
DB1
DB2
tDVKL
tKLDX
Note: tnVKH = tEVKH, tWVKH, etc. and tKHnX = tKHEX, tKHWX, etc.
JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan interface standard
(commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output drivers are powered by VDDQ.
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. TCK, TDI,
and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may
be left floating or tied to either VDD or VSS. TDO should be left unconnected.
Rev: 2.03 1/2005
20/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2002, GSI Technology, Inc.
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