GS8170DD36C Datasheet, PDF (12/29 Pages) GSI Technology – 18Mb Σ1x2Lp CMOS I/O Double Data Rate SigmaRAM

GS8170DD36C-333/300/250/200
DDR Late Write, Pipelined Read Truth Table
E1 E ADV W
CK _{(tn) (tn) (tn) (tn)}
Previous
Operation
Current Operation
DQ/CQ DQ/CQ DQ/CQ DQ/CQ
(t_n)
(t_n+½) (t_n+1) (t_n+1½)
0→1 X F
0
X
X
Bank Deselect
***/***
Hi-Z/Hi-Z
0→1 X X 1 X Bank Deselect Bank Deselect (Continue)
Hi-Z/Hi-Z
Hi-Z/Hi-Z
0→1 1 T
0
X
X
Deselect
***/***
Hi-Z/CQ
0→1 X X
1
X
Deselect
Deselect (Continue)
Hi-Z/CQ
Hi-Z/CQ
0→1 0 T
0
0
X
Write
Loads new address
***/***
D1/CQ D2/CQ
0→1 X X
1
X
Write
Write Continue
Increments address by 2
Dn-2/CQ Dn-1/CQ Dn/CQ Dn+1/CQ
0→1 0 T
0
1
X
Read
Loads new address
***/***
Q1/CQ Q2/CQ
0→1 X X
1
X
Read
Read Continue
Increments address by 2
Qn-2/CQ Qn-2/CQ Qn/CQ Qn+1/CQ
Notes:
1. If E2 = EP2 and E3 = EP3 then E = “T” else E = “F”.
2. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
3. “***” indicates that the DQ input requirement / output state and CQ output state are determined by the previous operation.
4. DQs are tri-stated in response to Bank Deselect, Deselect, and Write commands, one full cycle after the command is sampled.
5. CQs are tri-stated in response to Bank Deselect commands only, one full cycle after the command is sampled.
6. One (1) Continue operation may be initiated after a Read or Write operation is initiated to burst transfer a total of four (4) distinct pieces of
data per single external address input. If a second (2nd) Continue operation is initiated, the internal address wraps back to the initial exter-
nal (base) address.
Rev: 2.03 1/2005
12/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2002, GSI Technology, Inc.