GS8182S08 Datasheet, PDF (19/36 Pages) GSI Technology – 18Mb Burst of 2 SigmaSIO DDR-IITM SRAM

GS8182S08/09/18/36BD-400/375/333/300/250/200/167
AC Electrical Characteristics (Continued)
Parameter
-400
-375
-333
-300
-250
-200
-167
Symbol
Min Max Min Max Min Max Min Max Min Max Min Max Min Max
Hold Times
Address Input Hold Time
t_KHAX
0.4
—
0.4
— 0.4
—
0.4
—
0.5 — 0.6
—
0.7
— ns 1
Control Input Hold Time (RW, LD)
Control Input Hold Time (BWX,
NWX)
t_KHIX
0.4 — 0.4 — 0.4 — 0.4 — 0.5 — 0.6 — 0.7 — ns 2
t_IVKH
0.28 — 0.28 — 0.28 —
0.3
— 0.35 —
0.4
—
0.5
— ns 3
Data Input Hold Time
t_KHDX
0.28 — 0.28 — 0.28 —
0.3
— 0.35 —
0.4
—
0.5
— ns
Notes:
1. All Address inputs must meet the specified setup and hold times for all latching clock edges.
2. Control singles are RW, LD.
3. Control singles BW0, BW1, (NW0, NW1 for x8) and BW2, BW3 for x36.
4. If C, C are tied high, K, K become the references for C, C timing parameters.
5. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus contention because tCHQX1 is a MIN parameter
that is worst case at totally different test conditions (0°C, 1.9 V) than tCHQZ, which is a MAX parameter (worst case at 70°C, 1.7 V). It is not possible for two SRAMs on the same
board to be at such different voltages and temperatures.
6. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
7. V_DD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once V_DD and input clock are stable.
8. Echo clock is very tightly controlled to data valid/data hold. By design, there is a ±0.1 ns variation from echo clock to data. The datasheet parameters reflect tester guard bands
and test setup variations.
Rev: 1.03c 11/2011
19/36
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2007, GSI Technology