GS8182S08 Datasheet, PDF (12/36 Pages) GSI Technology – 18Mb Burst of 2 SigmaSIO DDR-IITM SRAM

GS8182S08/09/18/36BD-400/375/333/300/250/200/167
FLXDrive-II Output Driver Impedance Control
HSTL I/O SigmaSIO DDR-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected
to V_SS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be
5X the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching
with a vendor-specified tolerance is between 175Ω and 350Ω. Periodic readjustment of the output driver impedance is necessary as
the impedance is affected by drifts in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for
drifts in supply voltage and temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts
again. Each impedance evaluation may move the output driver impedance level one step at a time towards the optimum level.
Separate I/O Burst of 2 Sigma SIO-II SRAM Truth Table
A
LD
R/W
Current
Operation
D
D
Q
Q
K↑
K↑
K↑
K↑
(t_n)
(t_n)
(t_n)
(t_n)
K↑
(t_n+1)
K↑
(t_n+1)
K↑
(t_n+1)
K↑
(t_n+1)
X
1
X
Deselect
X
—
Hi-Z
—
V
0
1
Read
X
—
Q0
Q1
V
0
0
Write
D0
D1
Hi-Z
—
Notes:
1. “1” = input “high”; “0” = input “low”; “V” = input “valid”; “X” = input “don’t care”
2. “—” indicates that the input requirement or output state is determined by the next operation.
3. Q0 and Q1 indicate the first and second pieces of output data transferred during Read operations.
4. D0 and D1 indicate the first and second pieces of input data transferred during Write operations.
5. Qs are tristated for one cycle in response to Deselect and Write commands, one cycle after the command is sampled, except when pre-
ceded by a Read command.
6. CQ is never tristated.
7. Users should not clock in metastable addresses.
x18 Byte Write Clock Truth Table
BW
BW
Current Operation
K↑
K↑
K↑
(t_n+1)
(t_n+2)
(t_n)
T
T
Write
Dx stored if BWn = 0 in both data transfers
T
F
Write
Dx stored if BWn = 0 in 1st data transfer only
F
T
Write
Dx stored if BWn = 0 in 2nd data transfer only
F
F
Write Abort
No Dx stored in either data transfer
Notes:
1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
2. If one or more BWn = 0, then BW = “T”, else BW = “F”.
Rev: 1.03c 11/2011
12/36
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
D
K↑
(t_n+1)
D1
D1
X
X
D
K↑
(t_n+2)
D2
X
D2
X
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