GS816273CC Datasheet, PDF (17/28 Pages) GSI Technology – 256K x 72 18Mb S/DCD Sync Burst SRAMs

Pipeline Mode Timing (DCD)
Preliminary
GS816273CC-333/300/250
Begin Read A Cont
CK
Deselect Deselect Write B
tKL
tKH
tKC
Read C
Read C+1 Read C+2 Read C+3 Cont
ADSP
ADSC
ADV
Ao–An
GW
BW
Ba–Bd
E1
E2
E3
tS
tH
tS
tS
tH
A
tS
tS
tS
tH
tS
tH
tS
tH
ADSC initiated read
tH
B
C
tH
tH
tS
E2 and E3 only sampled with ADSC
G
DQa–DQd Hi-Z
tOE
tOHZ
Q(A)
tS
tH
D(B)
tKQ
tLZ
Q(C)
Q(C+1)
Q(C+2)
Deselect Deselect
Deselected with E1
Q(C+3)
tHZ
tKQX
Rev: 1.01a 6/2006
17/28
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2005, GSI Technology