GS816273CC Datasheet, PDF (15/28 Pages) GSI Technology – 256K x 72 18Mb S/DCD Sync Burst SRAMs

Preliminary
GS816273CC-333/300/250
AC Electrical Characteristics
Parameter
Symbol
-333
Min
Max
-300
Min
Max
-250
Unit
Min
Max
Pipeline
Clock Cycle Time
Clock to Output Valid
Clock to Output Invalid
Clock to Output in Low-Z
Setup time
Hold time
tKC
3.0
—
3.3
—
4.0
—
ns
tKQ
—
2.8
—
2.8
—
3.0
ns
tKQX
1.5
—
1.5
—
1.5
—
ns
tLZ¹
1.5
—
1.5
—
1.5
—
ns
tS
1.0
—
1.0
—
1.2
—
ns
tH
0.1
—
0.1
—
0.2
—
ns
Clock HIGH Time
tKH
1.0
—
1.0
—
1.3
—
ns
Clock LOW Time
tKL
1.2
—
1.2
—
1.5
—
ns
Clock to Output in
High-Z
tHZ¹
1.5
2.8
1.5
2.8
1.5
3.0
ns
G to Output Valid
tOE
—
2.8
—
2.8
—
3.0
ns
G to output in Low-Z
G to output in High-Z
tOLZ¹
tOHZ¹
0
—
0
—
0
—
ns
—
2.8
—
2.8
—
3.0
ns
ZZ setup time
ZZ hold time
tZZS²
tZZH²
5
—
5
—
5
—
ns
1
—
1
—
1
—
ns
ZZ recovery
tZZR
20
—
20
—
20
—
ns
Notes:
1. These parameters are sampled and are not 100% tested.
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
Rev: 1.01a 6/2006
15/28
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2005, GSI Technology