GS816273CC Datasheet, PDF (13/28 Pages) GSI Technology – 256K x 72 18Mb S/DCD Sync Burst SRAMs

AC Test Conditions
Parameter
Conditions
Input high level
V_DD – 0.2 V
Input low level
0.2 V
Input slew rate
1 V/ns
Input reference level
V_DD/2
Output reference level
V_DDQ/2
Output load
Fig. 1
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.
3. Device is deselected as defined by the Truth Table.
Preliminary
GS816273CC-333/300/250
Output Load 1
DQ
50Ω
30pF^*
V_DDQ/2
* Distributed Test Jig Capacitance
DC Electrical Characteristics
Parameter
Input Leakage Current
(except mode pins)
FT, ZZ Input Current
Output Leakage Current
DC Output Characteristics
Parameter
2.5 V Output High Voltage
3.3 V Output High Voltage
Output Low Voltage
Symbol
I_IL
I_IN
I_OL
Symbol
V_OH2
V_OH3
V_OL
Test Conditions
V_IN = 0 to V_DD
V_DD ≥ V_IN ≥ 0 V
Output Disable, V_OUT = 0 to V_DD
Test Conditions
I_OH = –8 mA, V_DDQ = 2.375 V
I_OH = –8 mA, V_DDQ = 3.135 V
I_OL = 8 mA
Min
–1 uA
–100 uA
–1 uA
Max
1 uA
100 uA
1 uA
Min
Max
1.7 V
—
2.4 V
—
—
0.4 V
Rev: 1.01a 6/2006
13/28
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2005, GSI Technology