GS81302R08 Datasheet, PDF (11/35 Pages) GSI Technology – 144Mb SigmaDDRTM-II Burst of 4 SRAM

GS81302R08/09/18/36E-375/350/333/300/250
Burst of 4 Nybble Write Clock Truth Table
NW
NW
NW
NW
Current Operation
D
K↑
(t_n+1)
K↑
(t_n+1½)
K↑
(t_n+2)
K↑
(t_n+2½)
T
T
T
T
T
F
F
F
K↑
(t_n)
Write
Dx stored if NWn = 0 in all four data transfers
Write
Dx stored if NWn = 0 in 1st data transfer only
K↑
(t_n+1)
D0
D0
F
T
F
F
Write
Dx stored if NWn = 0 in 2nd data transfer only
X
F
F
T
F
Write
Dx stored if NWn = 0 in 3rd data transfer only
X
F
F
F
T
Write
Dx stored if NWn = 0 in 4th data transfer only
X
F
F
F
F
Write Abort
No Dx stored in any of the four data transfers
X
Notes:
1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
2. If one or more NWn = 0, then NW = “T”, else NW = “F”.
D
K↑
(t_n+1½)
D2
X
D1
X
X
X
D
K↑
(t_n+2)
D3
X
X
D2
X
X
D
K↑
(t_n+2½)
D4
X
X
X
D3
X
Rev: 1.03b 12/2011
11/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology