GS81302R08 Datasheet, PDF (10/35 Pages) GSI Technology – 144Mb SigmaDDRTM-II Burst of 4 SRAM

GS81302R08/09/18/36E-375/350/333/300/250
Common I/O SigmaDDR-II Burst of 4 SRAM Truth Table
DQ
K_n
LD
R/W
A+0
A+1
A+2
↑
1
X
Hi-Z
↑
0
0
D@K_n+1
Q@K_n+1
↑
0
1
or
C_n+1
Note:
Q is controlled by K clocks if C clocks are not used.
Hi-Z
D@K_n+1
Q@K_n+2
or
C_n+2
Hi-Z
D@K_n+2
Q@K_n+2
or
C_n+2
A+3
Hi-Z
D@K_n+2
Q@K_n+3
or
C_n+3
Operation
Deselect
Write
Read
Burst of 4 Byte Write Clock Truth Table
BW
BW
BW
BW
Current Operation
D
K↑
(t_n+1)
T
K↑
(t_n+1½)
T
K↑
(t_n+2)
T
K↑
(t_n+2½)
T
K↑
(t_n)
Write
Dx stored if BWn = 0 in all four data transfers
K↑
(t_n+1)
D0
T
F
F
F
Write
Dx stored if BWn = 0 in 1st data transfer only
D0
F
T
F
F
Write
Dx stored if BWn = 0 in 2nd data transfer only
X
F
F
T
F
Write
Dx stored if BWn = 0 in 3rd data transfer only
X
F
F
F
T
Write
Dx stored if BWn = 0 in 4th data transfer only
X
F
F
F
F
Write Abort
No Dx stored in any of the four data transfers
X
Notes:
1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
2. If one or more BWn = 0, then BW = “T”, else BW = “F”.
D
K↑
(t_n+1½)
D2
X
D1
X
X
X
D
K↑
(t_n+2)
D3
X
X
D2
X
X
D
K↑
(t_n+2½)
D4
X
X
X
D3
X
Rev: 1.03b 12/2011
10/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology