GS8128036GT-200IV Datasheet, PDF (1/23 Pages) GSI Technology – 8M x 18, 4M x 32, 4M x 36 144Mb Sync Burst SRAMs

GS8128018/32/36GT-xxxV
100-Pin TQFP
Commercial Temp
Industrial Temp
8M x 18, 4M x 32, 4M x 36
144Mb Sync Burst SRAMs
333 MHz–200 MHz
1.8 V or 2.5 V V_DD
1.8 V or 2.5 V I/O
Features
• FT pin for user-configurable flow through or pipeline
operation
• Single Cycle Deselect (SCD) operation
• 1.8 V or 2.5 V +10%/–10% core power supply
• 1.8 V or 2.5 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• 6/6 RoHS-compliant 100-lead TQFP package
Functional Description
Applications
The GS8128018/36GT-xxxV is a 150,994,944-bit high
performance synchronous SRAM with a 2-bit burst address
counter. Although of a type originally developed for Level 2
Cache applications supporting high performance CPUs, the
device now finds application in synchronous SRAM
applications, ranging from DSP main store to networking chip
set support.
Controls
Addresses, data I/Os, chip enables (E1 and E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS8128018/36GT-xxxV operates on a 1.8 V or 2.5 V
power supply. All input are 1.8 V or 2.5 V compatible.
Separate output power (V_DDQ) pins are used to decouple
output noise from the internal circuits and are 1.8 V or 2.5 V
compatible.
Parameter Synopsis
Pipeline
3-1-1-1
Flow Through
2-1-1-1
t_KQ
tCycle
Curr (x18)
Curr (x32/x36)
t_KQ
tCycle
Curr (x18)
Curr (x32/x36)
-333 -250 -200 Unit
2.5
2.5
3.0
ns
3.0
4.0
5.0
ns
530 430 360 mA
580 460 390 mA
4.5
5.5
6.5
ns
4.5
5.5
6.5
ns
400 360 285 mA
420 380 320 mA
Rev: 1.01 5/2017
1/22
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2015, GSI Technology