GS2965 Datasheet, PDF (25/41 Pages) Gennum Corporation – Uses standard 27MHz crystal

the SDI input will latch data in on the rising edge of SCK. The SDO data output will
transition on falling edges of SCK. Data is transmitted or received on the SPI port MSB
first LSB last.
SCK
CS
Cycle #
1 2345678
SDI ^{z 1} 2 ^{3 4 5 6 7 8 z}
SDO ^{z 1 2 3 4 5 6 7 8 z}
Figure 4-4: Data Clock Alignment
4.15.5 Single Device Operation
For applications with a single device or applications with multiple devices where daisy
chaining is not desired, the chain position bits C[6:0] should always be set to 0. As a
by-product of the daisy chaining feature, Read and Write operations experience a 32
SCK cycle latency from SDI to SDO. For more details on daisy-chaining, refer to
Section 4.15.8 on page 29.
rw 0 0 R
A[4:0]
Read/
Write
Reset
Address
Figure 4-5: 16-bit Command Format
C _N[6:0] = `0000000’
Chain Position
GS2965 Multi-Rate SDI Reclocker with Equalization &
De-emphasis
Data Sheet
52462 - 4
July 2012
25 of 41
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