GS2965 Datasheet, PDF (17/41 Pages) Gennum Corporation – Uses standard 27MHz crystal

Table 4-1: Input Trace Equalization Operation
EQn_EN Setting
LOW
HIGH
Trace Equalization
Range
Low
Medium
The default peak-gain setting upon power-up is optimized for compensating the
high-frequency losses associated with approximately 10 inches of 5-mil stripline in FR4
material.
The EQn_EN pins are multiplexed with the serial host interface pins. The EQn_EN
functionality is enabled when pin HIF is tied high, as shown in Table 4-2:
Table 4-2: EQn_EN Pins Multiplexed
Pin
SDI/EQ0_EN
CS/EQ1_EN
Function
Active-high logic input to enable trace-equalization for high-speed input
channel 0.
Active-high logic input to enable trace-equalization for high-speed input
channel 1.
4.4 2:1 Input Mux
The GS2965 incorporates a 2:1 input mux, which allows the connection of two
independent streams of video/data. There are two differential inputs (DDI[1:0] /
DDI[1:0]). The active channel can be selected via the DDI_SEL[1:0] registers as shown in
Table 4-3.
Table 4-3: Input Selection Table
DDI_SEL[1:0]
00
01
10
11
* - Power up default
Selected Input
DDI0*
NOT VALID
NOT VALID
DDI1
Active circuitry associated with the input buffers and trace EQ can only be turned on for
the selected input. Inputs which are not selected have their input buffers and trace EQs
turned OFF to save power. Unused inputs can be either left floating, or tied to VCC.
GS2965 Multi-Rate SDI Reclocker with Equalization &
De-emphasis
Data Sheet
52462 - 4
July 2012
17 of 41
Proprietary & Confidential