GA04JT17-247 Datasheet, PDF (8/12 Pages) GeneSiC Semiconductor, Inc. – Normally – OFF Silicon Carbide Junction Transistor

GA04JT17-247
Ideally, I_G,pon should terminate when the drain voltage falls to its on-state value in order to avoid unnecessary drive losses during the steady
on-state. In practice, the rise time of the I_G,on pulse is affected by the parasitic inductances, L_par in the device package and drive circuit. A
voltage developed across the parasitic inductance in the source path, L_s, can de-bias the gate-source junction, when high drain currents begin
to flow through the device. The voltage applied to the gate pin should be maintained high enough, above the V_GS,sat (see Figure 7) level to
counter these effects.
A high negative peak current, -I_G,off is recommended at the start of the turn-off transition, in order to rapidly sweep out the injected carriers from
the gate, and achieve rapid turn-off. While satisfactory turn off can be achieved with V_GS = 0 V, a negative gate voltage V_GS may be used in
order to speed up the turn-off transition.
Two high-speed drive topologies for the SiC SJTs are presented below.
B:1: High Speed, Low Loss Drive with Boost Capacitor, GA03IDDJT30-FR4
The GA04JT17-247 may be driven using a High Speed, Low Loss Drive with Boost Capacitor topology in which multiple voltage levels, a gate
resistor, and a gate capacitor are used to provide fast switching current peaks at turn-on and turn-off and a continuous gate current while in
on-state. A 3 kV isolated evaluation gate drive board (GA03IDDJT30-FR4) utilizing this topology is commercially available for high and low-
side driving, its datasheet provides additional details about this drive topology.
Figure 24: Topology of the GA03IDDJT30-FR4 Two Voltage Source gate driver.
The GA03IDDJT30-FR4 evaluation board comes equipped with two on board gate drive resistors (RG1, RG2) pre-installed for an effective
gate resistance³ of R_G = 3.75 Ω. It may be necessary for the user to reduce RG1 and RG2 under high drain current conditions for safe
operation of the GA04JT17-247. The steady state current supplied to the gate pin of the GA04JT17-247 with on-board R_G = 3.75 Ω, is shown
in Figure 25. The maximum allowable safe value of R_G for the user’s required drain current can be read from Figure 26.
For the GA04JT17-247, R_G must be reduced for I_D ≥ ~8 A for safe operation with the GA03IDDJT30-FR4.
For operation at I_D ≥ ~8 A, R_G may be calculated from the following equation, which contains the DC current gain h_FE (Figure 6) and the gate-
source saturation voltage V_GS,sat (Figure 7).
,
4.7
,
1.5
,
0.6Ω
Nov 2014
http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/
Pg8 of 11