GA10JT12-CAL Datasheet, PDF (6/8 Pages) GeneSiC Semiconductor, Inc. – Normally – OFF Silicon Carbide Junction Transistor

Section VI: Mechanical Parameters
Raster Size
Area total / active
Thickness
Wafer Size
Flat Position
Passivation frontside
Pad Metal (Anode)
Backside Metal (Cathode)
Die Bond
Wire Bond
Reject ink dot size
Recommended storage environment
Section VII: Chip Dimensions
GA10JT12-CAL
2.10 x 2.10
mm²
83 x 83
mil²
4.41/3.31
mm²
6836/5134
mil²
360
µm
14
mil
100
mm
3937
mil
0
deg
0
deg
Polyimide
4000 nm Al
400 nm Ni + 200 nm Au -system
Electrically conductive glue or solder
Al ≤ 10 mil (Source)
Al ≤ 3 mil (Gate)
Φ ≥ 0.3 mm
Store in original container, in dry nitrogen,
< 6 months at an ambient temperature of 23 °C
A
DIE
B
C
SOURCE
D
WIREBONDABLE _E
F
GATE
G
WIREBONDABLE _H
mm
mil
2.10
83
2.10
83
1.47
58
1.52
60
0.17
7
0.40
16
0.30
12
0.30
12
NOTE
1. CONTROLLED DIMENSION IS INCH. DIMENSION IN BRACKET IS MILLIMETER.
2. DIMENSIONS DO NOT INCLUDE END FLASH, MOLD FLASH, MATERIAL PROTRUSIONS
Sept 2014
http://www.genesicsemi.com/high-temperature-sic/high-temperature-sic-bare-die/
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