MB85RS128A Datasheet, PDF (9/20 Pages) Fujitsu Component Limited. – Memory FRAM 128K (16 K x 8) Bit SPI

MB85RS128A
• READ
The READ command reads FRAM memory cell array data. Arbitrary 16 bits address and op-code of READ
are input to SI. The most significant address bit is invalid. Then, 8-cycle clock is input to SCK. SO is output
synchronously to the falling edge of SCK. While reading, the SI value is invalid. When CS is risen, the READ
command is completed, but keep on reading address with automatic increment is enabled by continuously
sending clock for 8 cycles each to SCK before CS is risen. When it reaches the most significant address, it
rolls over to come back to the starting address, and reading cycle keeps on infinitely.
CS
SCK
SI
SO
0 1 2 3 4 5 6 7 8 9 10 11 12 13
18 19 20 21 22 23 24 25 26 27 28 29 30 31
OP-CODE
16-bit Address
0 0 0 0 0 0 1 1 X X 13 12 11 10
543210
Invalid
MSB
High-Z
LSB _MSB
Data Out LSB
76543210
Invalid
• WRITE
The WRITE command writes data to FRAM memory cell array. WRITE op-code, arbitrary 16 bits of address
and 8 bits of writing data are input to SI. The most significant address bit is invalid. When 8 bits of writing
data is input, data is written to FRAM memory cell array. Risen CS will terminate the WRITE command, but
if you continue sending the writing data for 8 bits each before CS is risen, it is possible to continue writing
with automatic address increment. When it reaches the most significant address, it rolls over, comes back
to the starting address, and writing cycle can be continued infinitely.
CS
SCK
SI
SO
0 1 2 3 4 5 6 7 8 9 10 11 12 13
18 19 20 21 22 23 24 25 26 27 28 29 30 31
OP-CODE
16-bit Address
Data In
0 0 0 0 0 0 1 0 X X 13 12 11 10
543210 76543210
MSB
LSB MSB
LSB
High-Z
DS501-00008-0v01-E
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