MB15E03L Datasheet, PDF (9/25 Pages) Fujitsu Component Limited. – Single Serial Input PLL Frequency Synthesizer On-Chip 1.2 GHz Prescaler

MB15E03L
Table.4 Binary 7-bit Swallow Counter Data Setting
Divide
ratio
(A)
AAAAAAA
7654321
0
0000000
1
0000001
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
127
1111111
Note: • Divide ratio (A) range = 0 to 127
Table. 5 Prescaler Data Setting
SW
Prescaler Divide ratio
H
64/65
L
128/129
Table. 6 LD/fout Output Select Data Setting
LDS
LD/fout output signal
H
fout signal
L
LD signal
Relation between the FC input and phase characteristics
The FC bit changes the phase characteristics of the phase comparator. Both the internal charge pump output level
(DO) and the phase comparator output (φR, φP) are reversed according to the FC bit. Also, the monitor pin (fOUT)
output is controlled by the FC bit. The relationship between the FC bit and each of DO, φR, and φP is shown below.
Table. 7 FC Bit Data Setting (LDS = ”H”)
FC = High
Do
φR
φP
LD/fout
Do
fr > fp
H
L
L
L
fr < fp
L
H
Z*
fout = fr
H
fr = fp
Z*
L
Z*
Z*
* : High impedance
FC = Low
φR
φP
H
Z*
L
L
L
Z*
LD/fout
fout = fr
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