MB15E03L Datasheet, PDF (7/25 Pages) Fujitsu Component Limited. – Single Serial Input PLL Frequency Synthesizer On-Chip 1.2 GHz Prescaler

MB15E03L
s FUNCTION DESCRIPTIONS
1. Pulse Swallow Function
The divide ratio can be calculated using the following equation:
fVCO = [(M x N) + A] x fOSC ÷ R (A < N)
fVCO : Output frequency of external voltage controlled oscillator (VCO)
N : Preset divide ratio of binary 11-bit programmable counter (5 to 2,047)
A : Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127)
fOSC : Output frequency of the reference frequency oscillator
R : Preset divide ratio of binary 14-bit programmable reference counter (5 to 16,383)
M : Preset divide ratio of modules prescaler (64 or 128)
2. Serial Data Input
Serial data is processed using the Data, Clock, and LE pins. Serial data controls the programmable reference
divider and the programmable divider separately.
Binary serial data is entered through the Data pin.
One bit of data is shifted into the shift register on the rising edge of the clock. When the load enable pin is high,
stored data is latched according to the control bit data as follows:
Table.1 Control Bit
Control bit (CNT)
H
L
Destination of serial data
17 bit latch (for the programmable reference divider)
18 bit latch (for the programmable divider)
Shift Register Configuration
Programmable Reference Counter
(LSB)
(Data Flow)
(MSB)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
CR RR R R R R R R R R R R R
N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SW FC LDS
T
CNT : Control bit
R1 to R14: Divide ratio setting bit for the programmable reference counter (5 to 16,383)
SW : Divide ratio setting bit for the prescaler (64/65 or 128/129)
FC : Phase control bit for the phase comparator
LDS : LD/fout signal select bit
Note: Start data input with MSB first
[Table. 1]
[Table. 2]
[Table. 5]
[Table. 7]
[Table. 6]
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