MB15F86UL Datasheet, PDF (8/28 Pages) Fujitsu Component Limited. – Fractional-N PLL Frequency Synthesizer

MB15F86UL
s FUNCTIONAL DESCRIPTION
Serial Data Input
Serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of IF/RF-PLL
sections and programmable reference dividers of IF/RF-PLL sections are controlled individually.
Serial data of binary code is entered through Data pin.
On a rising edge of clock, one bit of serial data is transferred into the shift register. On a rising edge of load
enable signal, the data stored in the shift register is transferred to one of latches depending upon the control bit
data setting.
• Control Bit
The programmable
reference counter for
the IF-PLL
The programmable
counter and the
swallow counter for the
IF-PLL
The programmable
reference counter for
the RF-PLL
CN1
0
1
0
CN2
0
0
1
CN3
0
0
0
The prgrammable
counter and the
swallow counter for
the RF-PLL
1
1
0
Note : CN3 = 1 is prohibited
(1) Serial data format
LSB
12345
Direction of data shift
MSB
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0 0 0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 RC8 RC9 RC10 RC11 RC12 RC13 RC14 LDS T1 T2 SWC FCC CSC
1 0 0 AC1 AC2 AC3 AC4 0 0 0 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 X X
0 1 0 RF1 RF2 RF3 RF4 RF5 RF6 RF7 RF8 0 Q1 Q2 Q3 Q4 Q5 0 SC1 SC2 SWF FCF CSF
1 1 0 AF1 AF2 AF3 AF4 AF5 NF1 NF2 NF3 NF4 NF5 NF6 NF7 NF8 NF9 NF10 F1 F2 F3 F4 0
Control bit (CN3)
Control bit (CN2)
Control bit (CN1)
RC1 to RC14
AC1 to AC4
NC1 to NC11
LDS, T1, T2
SWC
FCC
CSC
RF1 to RF8
Q1 to Q5
AF1 to AF5
NF1 to NF10
F1 to F4
SC1, SC2
SWF
FCF
CSF
X
: Divide ratio setting bits for the reference counter of the IF (3 to 16383)
: Divide ratio setting bits for the swallow counter of the IF (0 to 15, A < N)
: Divide ratio setting bits for the programmable counter of the IF (3 to 2047)
: Select bits for the lock detect output or a monitoring phase comparison frequency
: Divide ratio setting for the prescaler of the IF
: Phase control bit for the phase detector of the IF
: Charge pump current select bit of the IF
: Divide ratio setting bits for the reference counter of the RF (3 to 255)
: Fractional-N increment setting bit (3 to 16)
: Divide ratio setting bits for the swallow counter of the RF (0 to 31, A < N − 2)
: Divide ratio setting bits for the programmable counter of the RF (18 to 1023)
: Fractional-N increment setting bit for the fractional accumulator (0 to 15, F < Q)
: Spurious cancel set bit of the RF.
: Divide ratio setting for the prescaler of the RF
: Phase control bit for the phase detector of the RF.
: Charge pump current select bit of the RF
: Dummy bit (Set “0” or “1”)
Note: Data input with MSB first.
8