MB15C02 Datasheet, PDF (8/25 Pages) Fujitsu Component Limited. – Single Serial Input PLL Frequency Synthesizer On-Chip prescaler

MB15C02
s FUNCTION DESCRIPTIONS
1. Pulse Swallow Function
The divide ratio can be calculated using the following equation:
fVCO = [(M × N) + A] × fOSC ÷ R (A < N)
fVCO : Output frequency of external voltage controlled oscillator (VCO)
N : Preset divide ratio of binary 12-bit programmable counter (5 to 4,095)
A : Preset divide ratio of binary 6-bit swallow counter (0 to 63)
fOSC : Output frequency of the reference frequency oscillator
R : Preset divide ratio of binary 14-bit programmable reference counter (5 to 16,383)
M : Preset modulus of dual modulus prescaler (64)
2. Circuit Description
(1) Intermittent operation
The intermittent operation of the MB15C02 refers to the process of activating and deactivating its internal circuit
thus saving power dissipation otherwise consumed by the circuit. If the circuit is simply restarted from the power
saving state, however, the phase relation between the reference frequency (fr) and the programmable frequency
(fp), which are the input to the phase comparator, is not stable even when they are of the same value. This may
cause the phase comparator to generate an excessively large error signal, resulting in an out-of-synth lock frequency
To preclude the occurrence of this problem, the MB15C02 has an intermittent mode control circuit which forces the
frequencies into phase with each other when the IC is reactivated, thus minimizing the error signal and resultant
lock frequency fluctuations. The intermittent mode control circuit is controlled by the PS pin. Setting pin PS high
provides the normal operation mode and setting the pin low provides the power saving mode. The MB15C02 behavior
in the active and power saving modes is summarized below.
Active mode (PS = “H”)
All MB15C02 circuits are active and provide the normal operation.
Power saving mode (PS = “L”)
The MB15C02 stops any circuits that consume power heavily as well as cause little inconvenience when deactivated
and enters the low-power dissipation state. Do, φR, φP, and LD pins take the same state as when the PLL is locked.
Do pin becomes a high-impedance state and the input voltage to the voltage control oscillator (VCO) is maintained
at the same level as in active mode(that is, locked state) according to a time constant of a low pass filter (LPF).
Consequently , the output frequency from the VCO (fvco) is maintained at approximately the lock frequency.
Applying the intermittent operation by alternating the active and power saving modes, and also forcing the phases
of fr and fp to synchronize when it switches from stand by to active modes, the MB15C02 can keep the power
dissipation of its entire circuitry to the minimum.
(2) Programmable divider
The fvco input through fin pin is divided by the programmable divider and then output to the phase comparator as
fp. It consists of a dual modulus prescaler, a 6-bit binary swallow counter, a 12-bit binary programmable counter,
and a controller which controls the divide ratio of the prescaler
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