MB15C02 Datasheet, PDF (12/25 Pages) Fujitsu Component Limited. – Single Serial Input PLL Frequency Synthesizer On-Chip prescaler

MB15C02
4. Setting the Divide Ratio
(1) Serial data format
The format of the serial data is shown is Figure 3. The serial data is composed of a control bit and divide ratio
setting data. The control bit selects the programmable divider or programmable reference divider.
In case of the programmable divider, serial data consists of 18 bits(6 bits for the swallow counter and 12 bits for the
programmable counter) and 1 control bit as shown in Figure 3.1. In case of the programmable reference divider,
the serial data consists of 14 divider bits and 1 control bit as shown in Figure 3.2.
The control bit is set to 0 to identify the serial data for the programmable divider and to 1 to select the serial data
for the programmable reference divider.
Figure 3. Serial data format
LSB
Direction of data input
MSB
C
A
0
A
1
A
2
A
3
A
4
A
5
N
0
N
1
N
2
N
3
N
4
N
5
N
6
N
7
N
8
N
9
NN
10 11
control bit
Swallow counter
Programmable counter
Figure 3.1. Divide ratio for the programmable divider
LSB
Direction of data input
MSB
C
R
0
R
1
R
2
R
3
R
4
R
5
R
6
R
7
R
8
R
9
RRRR
10 11 12 13
Programmable reference counter
control bit
Figure 3.2. Divide ratio for the programmable reference divider
12