MB15C02 Datasheet, PDF (14/25 Pages) Fujitsu Component Limited. – Single Serial Input PLL Frequency Synthesizer On-Chip prescaler

MB15C02
(4) Setting the divide ratio for the programmable reference divider
Columns R0-R13 of Table 3 represent the divide ratio of the programmable reference counter. The control bit is set
to 1.
Table.3 Divide ratio for the programmable reference divider
Divide
ratio
(R)
5
6
⋅
16383
RRRRRRRRRRRRRR
0 1 2 3 4 5 6 7 8 9 10 11 12 13
10100000000000
01100000000000
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
11111111111111
(5) Setting data input timing
The MB15C02 uses 19 bits of serial data for the programmable divider and 15 bits for the programmable reference
divider. When more bits of serial data than defined for the target divider are received, only the last valid serial data
bits are effective.
To set the divide ratio for the MB15C02 dividers, it is necessary to supply the Data, Clock, and LE signals at the
timing shown in Figure 5.
t1 (>1 µs): Data setup time
t2 (>1 µs): Data hold time t3 (> µs): Clock pulse width
t4 (>1 µs): LE setup time to the rising edge of last clock
t5 (>1 µs): LE pulse width
Data
Clock
LE
t2
t3
t4
t1
t5
Figure 5. Serial data input timing
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