CS101_07 Datasheet, PDF (8/12 Pages) Fujitsu Component Limited. – Standard Cell

CS101 Series
■ AC CHARACTERISTICS
Parameter
Symbol
Min
Value
Typ
Delay time
tpd *¹
typ *² × tmin *³ typ *² × ttyp *³
*1 : Delay time = propagation delay time, enable time, disable time
*2 : “typ” is calculated based on the cell specifications.
*3 : Measurement condition
Measurement condition
tmin
VDD = 1.2 V ± 0.1 V, VSS = 0 V, Tj = − 40 °C to +125 °C
0.62
Max
typ *² × tmax *³
ttyp
1.00
Note : The values are reference values, which vary depending on the cells.
Unit
ns
tmax
1.57
■ I/O PIN CAPACITANCE
Parameter
Symbol
Value
Input pin
CIN
Max16
Output pin
COUT
Max16
I/O pin
CI/O
Max16
Note : The capacitance values vary depending on the package and pin positions.
Unit
pF
pF
pF
■ DESIGN METHODS
Fujitsu Microelectronics’s Reference Design Flow provides the following functions that help shorten the devel-
opment time of large scale and high quality LSIs.
• High reliability design estimation in the early stage of physical design realized by physical prototyping.
• Layout synthesis with optimized timing realized by physical synthesis tools.
• High accuracy design environment considering drop in power supply voltage, signal noise, delay penalty, and
crosstalk.
• I/O design environment (power line design, assignment and selection of I/Os, package selection) considering
noise.
■ PACKAGES
Packages available for existing series can be used for CS101 series. This allows smooth replacement with
previously developed products.
Please contact your Fujitsu Microelectronics agent for details of delivery times.
FBGA package : Max 424 pins
FC-BGA package : Max 2116 pins
PBGA package : Max 420 pins
TEBGA package : Max 900 pins
(Packages under planning are included.)
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