CS101_07 Datasheet, PDF (2/12 Pages) Fujitsu Component Limited. – Standard Cell

CS101 Series
(Continued)
• Special interfaces (LVDS, SSTL2, others)
• Supports use of industry standard libraries (.LIB).
• Uses industry standard tools and supports the optimum tools for the application.
• Short-term development using a physical prototyping tool
• One pass design using a physical synthesis tool
• Hierarchical design environment for supporting large-scale circuits
• Support for Signal Integrity, EMI noise reduction
• Support for static timing sign-off
• Optimum package range : FBGA, FC-BGA, PBGA,TEBGA
Note : Items under development are included.
■ MACRO LIBRARIES (including those in preparation)
1. Logic cells (about 400 types)
Unit cell having three different types of core transistors with a different threshold value are provided.
• Adder
• AND
• AND-OR
• AND-OR Inverter
• Buffer
• Clock Buffer
• Decoder
• Delay Buffer
• ENOR
• EOR
• Inverter
• Latch
• NAND
• NOR
• OR
• OR-AND
• OR-AND Inverter
• SCAN Flip flop
• Non-SCAN Flip Flop • Selector
• Others
2. IP macros
Compliance with the design rules recommended by the industry standard STARC (Semiconductor Technology
Academic Research Center) recommendations which means a wide range of commercially available IP macros
can be used.
CPU/DSP
ARM core (ARM7TDMI-S/ARM946E-S/ARM1176JZF-S),
FR71E core, Peripherals IP
Mixed signal macro
ADC, DAC, OPAMP, others
Compiled macro
RAM (1-port, 2-port), ROM, product sum calculator, others
PLL
Analog PLL
3. Special I/O interface macro
Interface macro (PHY)
LVDS, SSTL2, SSTL18, PCI, I²C
Interface macro (Controller) USB2.0 Device/host, Serial ATA, PCI-Express, DDR2, HDMI, others
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